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Design, Fabrication, and Characterization of Monolithic 3D Ternary CMOS （M3D T-CMOS） Inverter

  • 안현호 (Hyunho Ahn, 서강대학교 일반대학원)

초록(요약문)

CMOS 반도체 소자는 수십 년간 무어의 법칙에 따라 지속적으로 발전해 왔으나, 130 nm technology node 이하에서부터, 단일 소자의 기생 성분보다 물리적인 interconnection 수의 증가가 RC delay에 더 지배적인 영향을 미치는 것으로 파악되었다. 이에 대한 해결책으로 삼차원 집적 공정이 도입되어, 금속 배선간 물리적 거리가 감소함에 따라 RC delay 특성이 일부 개선되었지만, 집적도 증가에 따른 interconnection 수 증가에 대한 근본적인 해결책이 되지는 못하였다. 또 다른 해결책으로는 다치 논리 도입을 통한 interconnection 감소가 제안되었다. 기존에 상용화된 이진 논리 체계가 삼진 논리 체계로 변환될 경우, 이론적으로 트랜지스터 개수가 37% 감소하여 interconnection 수를 감소시킬 수 있다는 장점이 있다. 그러나 기존에 제안된 삼진 반도체 소자들은 CMOS 공정 호환성, 동작 속도, 신호 잡음 마진 （SNM） 및 동작 전압 측면에서 각각의 한계를 지니고 있다. 본 학위논문에서는 이러한 한계를 극복하기 위해 MOSFET과 balance current transistor （BCT）가 monolithic 3D 형태로 수직 적층된 삼진 반도체 소자, M3D T-CMOS 소자 및 인버터를 제안하고 그 동작 특성을 검증하였다. 먼저, M3D T-CMOS 소자의 동작 원리 및 회로도 구성을 분석하였다. MOSFET은 high 및 low state 구현을 담당하고, BCT는 일정한 누설전류 공급을 통해 intermediate state를 구현한다. 두 소자의 gate를 독립적으로 제어하는 구조를 통해 p-type과 n-type M3D T-CMOS 소자를 직렬 연결한 인버터에서 VDD/2에서의 안정적인 intermediate state 구현이 가능함을 회로적 관점에서 규명하였다. 이어서, TCAD simulation을 기반으로 M3D T-CMOS 소자를 설계하였다. BCT에 적합한 소자 선정을 위한 비교 분석 결과, JLFET이 공정 재현성, 안정적인 전류 특성, 정밀한 전류 조절 측면에서 가장 적합함을 확인하였다. MOSFET의 Vth 및 JLFET의 채널 도핑 농도 설계를 통해 VDD 1 V 조건에서 SNM 142 mV 및 동작 주파수 568 MHz 수준의 명확한 3-state 동작이 가능함을 예측하였다. 다음으로, stacked channel 구조와 contact-in-contact （CIC） 공정을 핵심 공정 기술로 도입하여 M3D T-CMOS 소자를 제작하였다. 제작된 소자의 전기적 특성 평가를 통해 MOSFET과 BCT의 독립적인 동작 및 104 A 이상의 넓은 범위의 BCT 전류 제어가 가능함을 확인하였다. 제작된 M3D T-CMOS inverter의 전기적 특성 평가 결과, MOSFET의 낮은 Vth로 인해 설계 목표인 VDD 1 V 대비 높은 전압에서 3-state 동작이 구현되는 문제가 확인되었다. TCAD simulation calibration을 통해 TiN gate 도입에 의한 Vth 최적화 시 VDD 0.5 V의 낮은 전압 조건에서도 51.65 mV 이상의 SNM과 약 10 MHz 수준의 동작 속도가 기대됨을 확인하였으며, 기존 CMOS 호환 ternary inverter 대비 경쟁력 있는 SNM을 달성하였다. 마지막으로, TiN gate 도입의 효과를 실험적으로 검증하기 위해 planar DC T-CMOS 소자를 제작하였다. TiN gate 도입에 따른 Vth 증가를 확인하였으며, implantation damage에 의한 추가적인 Vth shift 문제가 확인되었다. 이는 buffer oxide 도입 등의 공정 최적화를 통해 해결 가능할 것으로 기대된다. 본 연구 결과는 M3D T-CMOS 소자가 기존 ternary logic 소자들의 한계를 극복하고, 저전압 고성능 삼진 논리 소자 실현 가능성을 제시하는 유망한 후보임을 시사한다.

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초록(요약문)

CMOS semiconductor devices have advanced continuously over several decades in accordance with Moore's Law. However, below the 130 nm technology node, the RC delay contribution from increasing physical interconnection count has been found to dominate over that arising from parasitic components of individual devices, becoming the primary bottleneck limiting chip operating speed. To address this issue, three-dimensional （3D） integration technology was introduced, which reduced the physical distance between metal interconnects and partially improved RC delay characteristics. Nevertheless, 3D integration did not constitute a fundamental solution to the increasing interconnection count accompanying higher integration density. As an alternative approach, the adoption of multi-valued logic （MVL） has been proposed as a means of reducing interconnection count. When the conventional binary logic system is replaced by a ternary logic system, the number of transistors is theoretically reduced by 37%, which consequently enables a reduction in interconnection count. However, previously proposed ternary semiconductor devices have each exhibited inherent limitations in terms of CMOS process compatibility, operating speed, signal noise margin （SNM）, and operating voltage. In this dissertation, a monolithic 3D ternary CMOS （M3D T-CMOS） device and inverter, in which a MOSFET and a balance current transistor （BCT） are vertically stacked in a monolithic 3D configuration, are proposed and experimentally demonstrated to address these limitations. First, the operating principle and circuit configuration of the M3D T-CMOS device are analyzed. The MOSFET is responsible for implementing high and low states, while the BCT generates a constant leakage current to realize the intermediate state. By independently controlling the gate electrodes of the two devices, it is demonstrated from a circuit perspective that a stable intermediate state at VDD/2 can be achieved in an inverter configured by connecting p-type and n-type M3D T-CMOS devices in series. Subsequently, the M3D T-CMOS device is designed based on TCAD simulation. Through comparative analysis of candidate devices for BCT implementation, JLFET is identified as the most suitable device in terms of process reproducibility, stable current characteristics regardless of drain voltage variation, and precise current controllability. By optimizing the MOSFET threshold voltage （Vth） and JLFET channel doping concentration, clear 3-state operation is predicted at VDD = 1 V, with an SNM of 142 mV and a maximum operating frequency of 568 MHz. Next, the M3D T-CMOS device is fabricated by introducing two key process technologies: a stacked channel structure for monolithic 3D integration and a contact-in- contact （CIC） process for equalizing the contact resistance between the MOSFET and BCT. Electrical characterization of the fabricated device confirms independent operation of the MOSFET and BCT, and demonstrates that the BCT current can be precisely controlled over a wide range exceeding 104 A through BCT gate voltage modulation. Electrical characterization of the fabricated M3D T-CMOS inverter reveals that 3- state operation is achieved only at a VDD significantly higher than the design target of 1 V, due to insufficient MOSFET Vth. Through TCAD simulation calibration, it is confirmed that Vth optimization via TiN gate introduction is expected to achieve an SNM exceeding 51.65 mV even at VDD = 0.5 V and a maximum operating frequency of approximately 10 MHz. Furthermore, the optimized device achieves a competitive SNM of 166 mV at VDD = 1.0 V and 141 mV at VDD = 0.9 V, compared to the 90–120 mV range reported by previously demonstrated CMOS-compatible ternary inverters. Finally, a planar DC T-CMOS device is fabricated to experimentally verify the effect of TiN gate introduction on T-CMOS inverter performance. An increase in Vth upon TiN gate adoption is confirmed, along with an additional Vth shift attributed to implantation damage introduced during the fabrication process. This issue is expected to be resolved through process optimization, such as the introduction of a buffer oxide prior to ion implantation, which is anticipated to enable the M3D T-CMOS inverter to achieve its design targets. These results demonstrate that the proposed M3D T-CMOS device is a promising candidate for overcoming the limitations of previously reported ternary logic devices, offering a viable pathway toward low-voltage, high-performance ternary logic operation.

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목차

Chapter 1. Introduction 1
1.1. Beyond Moore's law 1
1.2. Necessity of multi-valued logic (MVL) system 7
1.3. Various MVL devices 10
1.4. Scope and organization of dissertation 15
Chapter 2. Concept and operation principle of monolithic 3D ternary CMOS (M3D T-CMOS) devices and inverter 17
2.1. Definition of M3D T-CMOS devices and inverter 17
2.2. Operation principle of M3D T-CMOS devices and inverter 20
2.2.1. Operation principle of M3D T-CMOS devices 20
2.2.2. Operation principle of M3D T-CMOS inverter 22
2.3. Design detail of M3D T-CMOS devices and inverter 25
2.3.1. BCT design for M3D T-CMOS device and inverter 25
2.3.2. Gate bias condition of BCT for intermediate state 28
Chapter 3. M3D T-CMOS devices and inverter design based on TCAD simulation tool 30
3.1. Ideal design guideline of M3D T-CMOS inverter 30
3.2. TCAD simulation tool and physical models 33
3.3. Design of MOSFET threshold voltage 36
3.3.1. Structure parameters design of BCT 40
3.4. Characteristics of M3D T-CMOS devices and inverter 43
3.4.1. DC characteristics 43
3.4.2. AC characteristics 50
Chapter 4. Fabrication and electrical characterization of M3D T-CMOS device and inverter 56
4.1. Fabrication of M3D T-CMOS devices 56
4.2. Electrical characterization of M3D T-CMOS devices and inverter 63
4.2.1. Characteristics of M3D T-CMOS devices 63
4.2.2. Characteristics of M3D T-CMOS inverter 68
4.3. TCAD simulation-based optimization of M3D T-CMOS inverter 73
4.3.1. Calibration between TCAD simulation tool and measured data 73
4.3.2. Optimization of M3D T-CMOS inverter 77
Chapter 5. Experimental verification of optimized T-CMOS device design via planar structure 85
5.1. Fabrication of planar T-CMOS inverter 85
5.2. Electrical characterization of planar T-CMOS inverter 89
5.2.1. Transfer characteristic of MOSFET 89
5.2.2. Transfer characteristics of planar T-CMOS inverter 93
5.3. Performance Benchmark and Comparison 96
Chapter 6. Conclusion 100
Bibliography 103
List of Publications 108
Journals 108
Conferences 110
Patents 112

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