Design of 𝝅-T-Diode based High-Speed CMOS ESD I/O Protection Circuit
- 발행기관 서강대학교 일반대학원
- 지도교수 Jinho Jeong
- 발행년도 2026
- 학위수여년월 2026. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/sogang/000000082731
- UCI I804:11029-000000082731
- 본문언어 영어
- 저작권 논문은 저작권에 의해 보호받습니다.
목차
Abstract 6
1. Introduction 8
2. Analysis of Conventional ESD I/O Protection Circuits 11
2.1 All-pass T-Diode ESD I/O Protection Circuit 11
2.2 𝜋-Diode ESD I/O Protection Circuit 16
2.3 Bessel filter based ESD I/O Protection Circuit 21
3. Design of 𝝅-T-Diode with Power-Clamp ESD I/O Protection Circuit 28
3.1 Concept of the Proposed 𝜋-T-Diode Topology 28
3.2 𝜋-diode (𝐶𝐸𝑆𝐷/2) Design Parameter Selection 30
3.3 T-diode (𝐶𝐸𝑆𝐷/2) Design Parameter Selection 33
3.4 Comparison of 𝜋-T-Diode and Conventional ESD I/O Protection Topology 35
3.5 Circuit Design and Implementation 41
4. Measurement Results 49
4.1 S-parameters and Group delay 49
4.2 Eye diagram and BER Performance 52
4.3 ESD Robustness Performance 56
5. Conclusion 57
Reference 60
