A 68.2-dB SNDR 10-MHz BW 2nd Order Delta-Sigma Modulator Using Ring Amplifier based Integrators
- 주제(키워드) Analog-to-digital converter (ADC) , delta-sigma modulator , discrete-time (DT) , ring amplification , time-domain interpolation
- 발행기관 서강대학교 일반대학원
- 지도교수 Gil-Cho Ahn
- 발행년도 2026
- 학위수여년월 2026. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/sogang/000000082514
- UCI I804:11029-000000082514
- 본문언어 영어
- 저작권 논문은 저작권에 의해 보호받습니다.
초록(요약문)
This thesis presents a second-order single-loop discrete-time (DT) delta-sigma modulator (DSM) using ring-amplifier-based integrators. To relax the timing constraint for quantization and dynamic-element-matching (DEM) operation, the proposed DSM inserts a half-period delay into the feedback path. Additionally, the absence of a feedforward signal path alleviates signal attenuation at the quantizer input, relaxing the comparator accuracy requirement and enabling the use of a 5-bit flash quantizer without a preamplifier. In order to ensure linearity under the wide output swing introduced by the delayed feedback signal at the integrator inputs, both integrators are implemented with ring amplifiers. The prototype modulator is fabricated in a 28-nm CMOS process, occupying a core area of 0.079 mm². Operating from a 1.0 V supply at a 300 MHz clock frequency, it consumes 5.2 mW and achieves a 73 dB dynamic range (DR) and a peak signal-to-noise-and-distortion ratio (SNDR) of 68.2 dB, corresponding to a Schreier figure-of-merit (FoMS) of 161.04 dB.
more목차
Abstract
I. Introduction 11
Ⅱ. Overview of Delta-Sigma Modulator 14
2.1 Analog-to-digital converter 14
2.2 Delta-sigma Modulator basic 19
2.2.1 Oversampling 19
2.2.2 Noise shaping 22
Ⅲ. Proposed 2nd Order Delta-Sigma ADC 27
3.1 ADC Architecture 27
3.2 Ring Amplifier review 33
Ⅳ. Circuit Implementation 37
4.1 Proposed second-order DSM 37
4.2 Ring Amplifier based SC Integrators 40
4.3 5-bit Flash ADC with time-domain Interpolation 48
Ⅴ. Measurement Results 52
Ⅵ. Conclusion 58
Reference 59
