A 28-Gb/s Receiver with Phase Equalizing Continuous Time Linear Equalizer in 28-nm CMOS FDSOI Technology
- 발행기관 서강대학교 일반대학원
- 지도교수 Jinho Jeong
- 지도교수 정진호
- 발행년도 2025
- 학위수여년월 2025. 8
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제 URI http://www.dcollection.net/handler/sogang/000000081799
- UCI I804:11029-000000081799
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권 보호를 받습니다.
초록 (요약문)
This paper presents a continuous-time linear equalizer (CTLE) architecture that addresses the gain-phase trade-off issue commonly observed in high-speed serial receivers. As data rates approach 28-Gb/s and beyond, signal integrity degrades due to frequency- dependent attenuation and dispersion in long PCB traces, making equalization essential. Conventional CTLEs typically improve bandwidth by increasing gain peaking, but this often leads to significant phase distortion, degrading horizontal eye characteristics. To mitigate this, a novel CTLE incorporating a simple high-pass filter (HPF) structure is proposed. The HPF path introduces a zero near the original peaking frequency without additional power overhead, enabling high-frequency unity gain while suppressing sharp phase delay transitions. The two-stage CTLE is implemented in 28-nm CMOS FDSOI technology, and its performance is verified through simulation and measurement. The proposed design achieves a 3 dB bandwidth of 12.1 GHz and reduces phase delay variation from 24.5 ps to 11.6 ps. Eye diagram measurements confirm successful recovery of the eye opening, with an eye amplitude of 353 mV, a height of 116 mV, and a jitter of 13.2 ps under a 28 Gb/s PRBS-7 input. The equalizer occupies an active area of only 0.002 mm² and does not incur additional power consumption, demonstrating its practicality for compact, energy-efficient analog front-end systems in high-speed interconnects. Key words : Continuous time linear equalizer, boost factor, phase delay, peak-to-peak jitter
more목차
Abstract v
1. Introduction 1
2. Theory 3
2.1 Transmission line 3
2.1.1 Frequency-Dependent Distortion in Transmission Lines 3
2.1.2 Impact of Attenuation and Dispersion 7
2.1.3 Spectral Relevance of Phase Delay Variation 10
2.2 Continuous Time Linear Equalizer 12
2.2.1 Operating Principle of CTLE 12
2.2.2 Structural Limitations of CTLE 14
2.2.3 Simulation-Based Verification of CTLE Design Trade-off 15
2.2.4 Eye Diagram Simulation Considering Only Phase Characteristics 21
2.3 Previous equalizing techniques 22
3. Proposed CTLE Architecture 30
3.1 Operating Mechanism and Circuit Design 30
3.1.1 Operating Mechanism 30
3.1.2 Frequency-Domain Analysis 31
3.1.3 Circuit Design and Device Configuration 32
3.2 Simulation Results and Analysis 34
4. Measurement 37
4.1 Measurement Circuit 37
4.1.1 Input Matching Network 37
4.1.2 Output Matching Network 39
4.2 Measurement setup 42
4.2.1 Fabrication 42
4.2.2 Measurement environment 44
4.3 Measurement result 46
5. Conclusion 51
Reference 52
