Design of Wide-Range All-Digital Phase-Locked loop for Content-Addressable-Memory
- 주제어 (키워드) High-Speed , AD-PLL
- 발행기관 서강대학교 일반대학원
- 지도교수 범진욱
- 발행년도 2025
- 학위수여년월 2025. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제 URI http://www.dcollection.net/handler/sogang/000000079841
- UCI I804:11029-000000079841
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권 보호를 받습니다.
초록 (요약문)
This paper proposes an All-Digital PLL (ADPLL) designed to support Nano-Electro-Mechanical (NEM) associative memory and a Read-out Ring-Vernier Type TDC for enabling in-memory computing operations. The proposed ADPLL operates within a frequency range of 4.1 GHz to 6.75 GHz and achieves stable locking across a wide range of frequencies. To realize the resolution of the Ring-Vernier Type TDC, two clock signals with different speeds are supplied via the PLL, and the frequency of each clock is determined by adjusting the divider ratio. Prior to circuit design, Verilog behavioral simulation and MATLAB modeling were employed to analyze the loop system, enabling optimization of the ADPLL’s bandwidth and noise performance. Based on this analysis, the optimal digital loop filter gain was determined, and the ADPLL's performance was predicted. The proposed ADPLL circuit was fabricated using Samsung's 28nm LPP process, with the chip occupying an effective area of 0.017mm², excluding the power capacitor. The total supply voltage is 1.0 V, and the power consumption is measured at 8mW when locked to a center frequency of 4.88 GHz and 10mW at a center frequency of 6.1 GHz.
more초록 (요약문)
본 논문은 Nano-Electro-Mechanical(NEM) 연상형 메모리와 Read-out Ring-Vernier Type TDC가 In-memory-computing 연산을 구현하도록 돕는 ALL-Digital PLL(ADPLL)을 제안한다. 제안된 AD-PLL은 4.1GHz에서 6.75GHz의 동작 주파수를 가지며, Wide range에서 PLL이 다양한 주파수에 안정적으로 lock 할 수 있다. Ring-Vernier Type TDC의 resolution을 구현하기 위해 두 가지 속도의 clock이 PLL을 통해 공급되며, 각 clock의 주파수는 Divider의 ratio를 바꿔서 결정된다. 설계에 앞서 Verilog Behavioral Simulation과 Matlab을 통해 Loop system을 모델링 함으로써 AD-PLL의 Optimal 한 Bandwidth와 Noise 분석 을 수행했고, 이 분석을 기반으로 최적의 Digital Loop Filter gain과 ADPLL 의 Performance를 예측할 수 있었다. 제안된 AD-PLL은 Samsung 28nm LPP 공정으로 제작되었으며, Chip은 Power Cap을 제외하고 0.017mm2의 유효 면적을 차지한다. 전체적인 공급전압은 1.0V이며, 총 소모 전력은 4.88GHz 중심 주파수 고정 시 8mW, 6.1GHz 중심 주파수 고정 시 10mW이다.
more목차
Chapter 1. Introduction 1
Chapter 2. Background on All-Digital PLL 6
2.1 A Study on the Theory of PLL 6
2.2 Building and Functional Blocks of ADPLL 10
2.2.1 BBPD (Bang-Bang PD) 10
2.2.2 TDC (Time to Digital Converter 11
2.2.3 DLF (Digital Loop Filter) 15
2.2.3 DCO (Digital Controlled Oscillator) 18
Chapter 3. Proposed of All-Digital PLL 21
3.1 Design Consideration 21
3.2 Proposed Overall Architecture 22
3.3 Circuit implementation 26
3.3.1 PFD-TDC 26
3.3.2 DLF 28
3.3.3 DCO 29
3.4 Noise Analysis of ADPLL 32
3.4.1 S-domain model 32
3.4.2 Noise Analysis 37
Chapter 4. Measurement and Simulation Results 42
4.1 Transient Analysis 42
4.1.1 PFD-TDC operation 42
4.1.2 Phase noise of DCO 43
4.1.3 Operation of PLL locking 45
4.2 Measurement Environment and Chip 47
4.3 Noise Performance 49
4.3.1 Free Running DCO 49
4.3.2 Measurement Equipment error 52
4.3.3 PLL Performance 55
4.4 Performance Summary 64
Chapter 5. Conclusion 66
References 68
