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D-band Low-Noise Amplifier with High Linearity and Low Power Consumption Using Adaptive Bias in 90-nm SiGe BiCMOS Technology

초록 (요약문)

This paper presents a D-band (110–170 GHz) low-noise amplifier (LNA) implemented in 90-nm BiCMOS technology for 6G mobile communication. Unlike conventional 4G/5G systems, massive multiple-input multiple-output (MIMO) and full- duplex communication architectures demand both low power consumption and enhanced linearity. The proposed LNA comprises three stages, combining common emitter and cascode configurations. To achieve low power consumption, the final stage operates in deep class-AB, while linearity is improved through the integration of an adaptive bias circuit. The proposed bias circuit incorporates a diode-connected transistor and a shunt capacitor, which effectively mitigate amplifier distortion caused by rectification under high input power conditions. Measurements show a 3-dB bandwidth of 126–149.5 GHz, with a maximum small-signal gain of 18.5 dB and a minimum noise figure (NF) of 6.0 dB. The input 1-dB compression point (IP1dB) is –25 dBm, with a total DC power consumption of 14.5 mW. The fabricated chip, including pads, occupies an area of 0.73 mm × 0.59 mm.

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목차

1. Introduction 1
2. Circuit Design 3
2.1 90-nm SiGe BiCMOS Technology 3
2.2 Low-Noise Amplifier 6
2.3 Adaptive Bias Circuit 15
3. Fabrication and Measurement 20
4. Redesign 27
5. Conclusion 30
Reference 31

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