Dual-Residue-Based High-Speed Pipelined Analog-to-Digital Converters
- 주제어 (키워드) Analog-to-Digital Converter , Pipelined ADC , High-speed ADC
- 발행기관 서강대학교 일반대학원
- 지도교수 안길초
- 발행년도 2025
- 학위수여년월 2025. 2
- 학위명 박사
- 학과 및 전공 일반대학원 전자공학과
- 실제 URI http://www.dcollection.net/handler/sogang/000000079616
- UCI I804:11029-000000079616
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권 보호를 받습니다.
초록 (요약문)
This thesis proposes two high-speed ADC architectures using the dual-residue method: a 10-bit 500MS/s ADC and a 12-bit 150MS/s ADC. Both designs employ the dual-residue technique to achieve high-speed performance while reducing the complexity of the inter-stage residue amplifier and eliminating the need for reference full-scale matching calibration between stages. In Section III, a calibration free 10-bit 500MS/s three-stage dual-residue architecture is presented. A dual-residue method with single amplifier method enables to employ low-cost open-loop amplifier without gain calibration. Furthermore, simple current mirror-based residue amplifier is also adopted to minimize the residue amplifier cost. The ADC proposes current-mode dual-residue transferring technique and extended its stages to increase the sampling rate. The prototype ADC fabricated in a 28nm process achieves an SNDR of 50.3dB while consuming 7.86 mW under a 1.0V supply without any calibration. In Section IV, a voltage-time hybrid domain pipelined ADC is presented. The proposed ADC employs a voltage-domain SAR quantizer for the coarse stage to ensure linearity, while a time-domain quantizer is used for the fine stage to improve power efficiency. A hybrid domain dual-residue method is proposed to generate reference-embedded time-domain residues. It efficiently ensures full-scale matching between the converted time-domain residue and the time-domain reference of the fine stage. For the fine stage sub-quantizer, an interpolating TDC suited for dual-residue quantization is employed without using an external time-domain reference. A prototype ADC, implemented in a 40nm CMOS process, occupies 0.034mm². Operating at a sampling rate of 150 MS/s, the ADC achieves a SNDR of 61.1dB and a SFDR of 75.5dB at a Nyquist input, while consuming 2.54mW, resulting in a Walden FoM of 18.3fJ/conv.-step.
more목차
I. Introduction 1
II. Pipelined ADC 3
2.1. Basic architecture and operation of the pipelined ADC 3
2.2. Key building blocks of the pipelined ADC 7
2.2.1. Residue amplifier 7
2.2.2. Sub-quantizer 9
2.3 Basic architecture and operation of the dual-residue pipelined ADC 15
III. A calibration free three-stage 10-bit 500MS/s dual-residue pipelined-SAR ADC using current-mode backend 18
3.1. Introduction 18
3.2. Proposed architecture 19
3.3. Circuit implementation 22
3.3.1. 1st stage 2-bit/cycle SAR ADC 22
3.3.2. 2nd stage current-mode interpolating SAR ADC 25
3.3.3. RA2 and 3rd current-mode interpolating SAR ADC 31
3.3.4. Relative gain mismatch between dual residues 33
3.4. Measurements results 35
IV. A voltage-time hybrid domain pipelined ADC with dual-residue-based reference-embedded time residues 42
4.1. Introduction 42
4.2. Utilizing dual-residue method for voltage-time hybrid domain pipelined ADC 44
4.3. Proposed architecture 48
4.4. Circuit implementation 52
4.4.1. Coarse SAR ADC 52
4.4.2. Two-step voltage-to-time converter 55
4.4.3. Fine stage TDC 66
4.5. Mismatch errors from ITCs 71
4.6. Measurement results 78
V. Conclusion 87
References 88
