A 0.076 pJ/b/dB 10 Gb/s Adaptable NRZ Equalizer using Inverter-Based CTLE and Half-Rate Unrolled DFE in 28-nm CMOS
- 주제어 (키워드) High-speed interface , adaptable equalizer , inverter-based , half-rate , unrolled DFE
- 발행기관 서강대학교 일반대학원
- 지도교수 범진욱
- 발행년도 2025
- 학위수여년월 2025. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제 URI http://www.dcollection.net/handler/sogang/000000079460
- UCI I804:11029-000000079460
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권 보호를 받습니다.
초록 (요약문)
This paper proposes an inverter-based adaptable front-end for display interfaces. The proposed equalizer consists of an inverter-based continuous-time linear equalizer (CTLE) and an inverter-based half-rate unrolled decision feedback equalizer (DFE), demonstrating reliable operation at data rates of up to 10 Gb/s. The proposed inverter-based CTLE achieved gain boosting of up to 4.3 dB at 5 GHz and 13 dB at 12 GHz. The DFE timing constraint allows for an overall operation data rate of 10 Gb/s. The proposed architecture compensates for up to 30.3 dB channel loss, including a 2-m HDMI cable, HDMI breakout adapter, and FR4 trace. The prototype chip achieved a BER condition of BER<1E-12 while consuming 23.09 mW, corresponding to a power efficiency of 2.31 pJ/b. Taking into account channel loss variations due to different HDMI cable lengths, the design achieved an outstanding FoM of 0.076 pJ/b/dB at a channel loss of 30.3 dB. The proposed architecture, unlike conventional CML-type equalizers, employs an inverter-based approach, which eliminates the need for area-hungry passive inductors while achieving bandwidth extension. As a result, this design achieved an extremely small active area of 0.007 mm^2. The prototype chip for measurement was fabricated in 28-nm CMOS process.
more목차
1. Introduction 3
2. Background 7
2.1. Channel Bandwidth Limitation and Inter-Symbol Interference 7
2.1.1. Pseudo Random Binary Sequence 7
2.1.2. Return to Zero and Non-Return to Zero Data 13
2.1.3. Channel Frequency Response and Effect of Bandwidth Limitation 16
2.1.4. Effect of Noise on Bit Error Rate 20
2.2. Receiver Equalization 27
2.2.1. Concept of Equalization 27
2.2.2. Various Channel Loss and Equalizer Adaptation 30
2.2.3. Conventional Implementation of Continuous-Time Linear Equalizer 41
2.2.4. Conventional Implementation of Decision Feedback Equalizer 45
2.3. Reflection and Termination 55
3. Proposed Inverter-Based CTLE and DFE 59
3.1. Inverter-Based Analog Circuit 59
3.2. Inverter-Based Active Inductor 65
3.3. Proposed Inverter-Based CTLE 71
3.3.1. Inverter-Based CTLE Topology 71
3.3.2. Proposed Inverter-Based CTLE Architecture 73
3.3.3. CTLE Offset Calibration 78
3.4. Proposed Inverter-Based Half-Rate Unrolled DFE 80
3.4.1. Inverter-Based Unrolled Summer 80
3.4.2. StrongArm Slicer and AMUX Gate Control 82
3.4.3. StrongArm Slicer Input-Referred Offset and Noise 87
3.4.4. Clock Buffer and Data Buffer 89
3.4.5. Proposed Half-Rate Unrolled DFE Architecture 91
3.5. Overall Architecture of Proposed Inverter-Based Analog Front-End 93
4. Post-Layout Simulation Result 95
4.1. Layout Result of Overall Architecture 95
4.2. Channel Response 96
4.3. CTLE Simulation Result 98
4.4. DFE Simulation Result 100
5. Measurement Result 106
6. Conclusion 117
Reference 118
