Comparative Study on Bandwidth and Eye Diagram Performance in CMOS ESD Protection I/O Pads with Inductive Peaking Techniques
- 발행기관 서강대학교 일반대학원
- 지도교수 정진호
- 발행년도 2024
- 학위수여년월 2024. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/sogang/000000077247
- UCI I804:11029-000000077247
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권 보호를 받습니다.
초록
When designing CMOS ESD protected I/O pads, crucial performance metrics include wide bandwidth, flat group delay, wide eye opening, and ESD robustness. For data transmission in the range of tens of Gb/s, a bandwidth corresponding to 0.7 times the data rate is desired to minimize ISI. Additionally, flat group delay up to the Nyquist frequency guarantees wide eye opening performance. This paper compares the bandwidth, group delay, and eye opening performance of ESD protected I/O pads using inductive peaking techniques. Four inductive peaking techniques (T-diode, Modified T-diode, Pi-diode, and Bessel-like filter) are employed to design and fabricate ESD protected I/O pads in 28-nm LPP CMOS technology. To minimize circuit area, the layout of all circuits are implemented using pad-surrounding inductors. The performance metrics of each circuit, including bandwidth, group delay variation, and eye opening, are compared through simulation and measurement results at data rates of 28 Gb/s and 56 Gb/s. The paper also compares the bandwidth, group delay variation, and eye opening performance of the T-diode based on the coupling factor (k) through simulation and measurement results. Simulation and measurement results confirm that eye opening performance correlates with both bandwidth and group delay variation. Furthermore, an ESD-protected I/O pad should possess sufficient ESD current handling ability. We designed an ESD protected I/O pad to sustain 2 kV HBM (Human Body Model) stress. As I/O pads can be stressed by positive or negative ESD with grounded V_DD or V_SS, the ESD-protected I/O pad should provide ESD current paths for all possible combinations, including positive I/O to V_DD (PD), positive I/O to V_SS (PS), negative I/O to V_DD (ND), and negative I/O to V_SS (NS). Thus, we design and fabricate ESD protected I/O pads using three methods: single diode, dual diode, and dual diode with power clamp circuit. We compare the bandwidth and ESD robustness between the three methods through simulation and measurement results, and analyze the results based on an equivalent model. Finally, we compare the simulated bandwidth, group delay and eye opening performance of conventional T-diode, i.e., All-pass T-diode, according to the coupling factor k. In addition, we design eye optimized and miniaturized T-diode using a pad-surrounding inductor and compare its performance with All-pass T-diode.
more목차
1. Introduction 1
2. Performance comparison between inductive peaking topologies 4
1) Design of Inductive Peaking Topologies for ESD protected I/O pad 4
2) Layout Design 19
3) Performance Comparison with Simulation Results 22
4) Performance Comparison with Measurement Results 29
3. Design of whole chip ESD protected I/O pad 38
1) ESD Protected I/O pad with Single Diode 38
2) ESD Protected I/O pad with Dual Diode 42
3) ESD Protected I/O pad with Dual Diode and Power Clamp Circuit 46
4. Miniaturized and Eye optimized T-diode 51
1) Design of All-pass T-diode 51
2) Design of Miniaturized and Eye optimized T-diode 53
3) Performance Comparison with Simulation results 54
4) Performance Comparison with Measurement results 57
5. Conclusion 64
Reference 65
