Investigation of Device Performance for Fin Angle Optimization in FinFET and Gate-All-Around FETs for 3 nm-Node and Beyond
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주제(키워드) 도움말
FinFETs
, Logic gates
, Performance evaluation
, Market research
, Shape
, Electrostatics
, Electric potential
, 3-nm FinFET
, advanced logic technology
, capacitance components
, fin angle variation
, gate-all-around (GAA) FET
, low VDD
, nanosheet (NS) FET
, nano-wire (NW) FET
, technology computer-aided design (TCAD)
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발행기관
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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발행년도
2022
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총서유형
Journal
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본문언어
영어
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