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Design of Wideband ESD Protected I/O Pad using Pad-Stacked Inductor

초록 (요약문)

In this paper, we design and fabricate compact broadband ESD-protected I/O pad applicable to high-speed interface using the pad-stacked inductor. Conventional broadband ESD-protected I/O pad increases the size of the I/O pad circuit due to the inductor for bandwidth extension, which greatly increases the chip size of the high-speed interface with a large number of I/O pads. Therefore, in this study, we propose the broadband ESD-protected I/O pad using the pad-stacked inductor to reduce the area used as an inductor. When the I/O pad is stacked on the inductor, the vertical spacing with the inductor is very close, so the eddy current is strongly induced in the I/O pad, which reduces the inductance of the pad-stacked inductor at high frequencies, resulting in performance degradation. To alleviate the effect of eddy current, methods of designing the pad-stacked inductor and selecting a metal layer of the inductor are proposed. In addition, the performance degradation due to eddy current is further improved by inserting slots that interfere with the flow of eddy current in the corner of the pad rather than the conventional I/O pad. Finally, the π-diode is designed for the broadband ESD-protected I/O pad using the pad-stacked inductor. The designed π-diode using the pad-stacked inductor is fabricated in a 28-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology and measured in the 0.1-40 GHz band using VNA. The measurement result shows that bandwidth meeting |S11| < -10 dB is extended to 26.5 GHz and 3-dB gain (|S21|) bandwidth to 22.9 GHz. The eye-opening characteristics are excellent in the simulated eye diagram using the measured S-parameters at a data rate of 32 Gb/s. T-diode is also designed using the pad-stacked inductor, and the simulated result shows 3-dB bandwidth of 61.3 GHz, while meeting the OIF-CEI 56G mask limit for return loss.

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