서강대학교

Abstract

As wireless communication technology advances, the demand for analog-to-digital converters (ADCs) with wider bandwidth (BW) and higher dynamic range (DR) continues to grow [1]. Advances in the scaled-down process technology increase the cut-off frequency of metal-oxide-semiconductor field-effect transistors (MOSFET) and thus broaden the bandwidth of delta-sigma ADCs, making them a good candidate for these applications. Discrete-time (DT) delta-sigma ADCs based on switched-capacitor (SC) integrators have also been widely used due to their robust operation with accurate loop filter transfer function against process, voltage, temperature (PVT) fluctuations and low sensitivities to clock jitter. This thesis proposes a single-loop third-order delta-sigma ADC architecture using a source-follower (SF) based open-loop integrator to optimize power consumption [5]. By using the proposed source-follower integrator structure, the operating speed is increased efficiently compared to that found in conventional integrators. Two prototype chips are implemented to verify the efficacy of the proposed design techniques. A single-loop third-order 10-MHz bandwidth source-follower integrator based DT delta-sigma ADC is proposed and fabricated in a 65-nm CMOS process. It achieves a signal-to-noise-and-distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 73.3 dB and 89.2 dB, respectively. In addition, a third-order wideband delta-sigma ADC using a double-sampling source-follower integrator is proposed and fabricated in a 28-nm fully depleted silicon on insulator (FDSOI) CMOS process. In the simulation results, it achieves SNDR and SFDR of 69.8 dB and 71.8 dB, respectively, within the 80-MHz signal bandwidth.