A Study on Programmable System-on-Chip Implementation of a Wearable Ultrasound Bladder Monitoring System
- 주제(키워드) Medical ultrasound imaging , medical ultrasound system on SoC , Zynq Implementation , SIMD operation using NEON intrinsic , parallel computing , Dual-Core processing
- 발행기관 서강대학교 일반대학원
- 지도교수 유양모
- 발행년도 2021
- 학위수여년월 2021. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- UCI I804:11029-000000065953
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권보호를 받습니다.
초록/요약
Highly increasing focus on quality of life, the needs of connected healthcare is vastly emerging. This trend has brought a number of new applications of monitoring a patient’s health condition in real time. Medical ultrasound imaging has several advantages over other imaging modalities: it displays images in real time without ionizing radiation, costs an affordable price and is physically portable. This shows that ultrasound systems are suitable for this current trend of patient-centered wearable health care system. For managing urination disorders, it is important to routinely measure the bladder volume. Recently developed portable ultrasound devices can periodically measure the bladder volume. However, they are not suitable for bladder monitoring in point-of-care settings due to their size, price and usability. For bladder monitoring, wearable ultrasound devices can be attached to the lower part of the patient’s abdomen to continuously measure the bladder volume. In this paper, a programmable system-on-chip (SoC) solution to minimize the size and cost of a wearable bladder ultrasound imaging system is proposed. In the proposed programmable SoC solution, the recently introduced processing platform (Zynq-7000 family, Xilinx Inc.) where, in addition to a 28-nm-flexible programmable gate array (FPGA) module, a dual ARM Cortex-A9 MPcore processing module is integrated. The core ultrasound signal and image processing blocks for a wearable bladder monitoring system were implemented on the dual ARM Cortex-A0 Mpcore processor by using SIMD parallel processing with NEON intrinsic and dual-core processing. For generating an ultrasound bladder image, with parallel programming with NEON intrinsic on a dual-core processor, it takes less than 98.21 ms, resulting in >10 frames/s. The results showed that the proposed programmable SoC solution can reconstruct a real-time bladder ultrasound image with the minimum hardware and software resources.
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