서강대학교

초록/요약

In this study, terahertz (THz) on-chip antenna array using 65-nm complementary metal-oxide semiconductor (CMOS) process is proposed. The on-chip antenna is essential to connect with THz monolithic integrated circuits (TMICs) without the effect of parasitic components (impedance miss-matching and loss). And also, it is easy to fabricate with circuit. However, it has some disadvantages such as low radiation efficiency and narrow-bandwidth caused by thin silicon oxide (SiO2) substrate of CMOS process. Thus, the design direction for maximum performance is presented and defected ground structure (DGS) and parasitic resonator is used to improve the characteristic of on-chip single antenna in this study. The array structure is used to improve the gain, and the characteristic of antenna is comprised according to the array interval to optimize. Intentional impedance miss-matching is used to obtain wide-bandwidth of the antenna array. At 300 GHz of the single antenna and 1×2, 2×2 antenna array, the simulated gains are 5.3 dBi, 7.2 dBi and 8.8 dBi, and the fractional bandwidth is 6.0%, 14.7% and 19.3%, respectively. Approximately 2.7 dB of the gain is improved using the 1×2 array structure in the single antenna. The further away the array interval at the 1×2 antenna array, the directivity and gain is increased. The directivity of the 2×2 antenna array is higher than the directivity of the 1×2 antenna array, but there is a reduction of the radiation efficiency caused by loss of feed line. Therefore, the gain of the 2×2 antenna array has not improved much. Designed antenna which the single antenna, 1×2, 2×2 antenna array are fabricated by using 65-nm CMOS process, and measured by the THz antenna measurement setup. At 300 GHz of the single antenna and 1×2, 2×2 antenna array, the measured gain is 3.1 dBi, 7.2 dBi and 8.2 dBi, respectively. The measured gains are lower than simulation result because of the insertion loss of the RF pad. Also, measured gain of single antenna is further decreased by leakage power in the silicon (Si) substrate and analyzed for the reason for this loss using a 3-D simulator. The tendency to increase gains when using array structures in the single antenna and when the array interval goes further and when using the 2×2 array structure in the 1×2 array structure is very similar to the simulation. The additional processes such as dielectric resonator (DR) and silicon lens are used to improve the characteristic of antenna in the existing reported studies. On the contrary, in this study, the DGS and parasitic resonators are used to improve the on-chip antenna itself without additional processes, and the antenna array is designed to improve the gain. The fabricated 2×2 antenna array has 8.2 dBi of the measured gain at 300 GHz and 28.0% (246 – 330 GHz) of the measured bandwidth.