서강대학교

초록/요약

This paper proposes a low-power column-parallel Two-Step Single Slope Analog-to-Digital Converter (SS ADC) and voltage range tuned ramp generator for low-power CMOS Image Sensors (CIS). The proposed SS ADC has small bandwidth to drive the low power CMOS Image Sensors, without sacrificing the bandwidth performance. The ADC errors caused by the limited bandwidth can be resolved using dual CDS (Correlated Double Sampling) and using voltage range tuned ramp generator. The proposed Two-Step structure consists of a resistor DAC (coarse ramp) and a current DAC (fine ramp). The fine ramp has one slope generator, regardless of results of coarse ramp decisions, to remove the mismatch of slope between fine ramp slopes. This sensor of 960 × 720 pixels has been fabricated with 90 nm CMOS process. The measurement results demonstrate that proposed column parallel CDS circuits can achieve the current consumption is about 2 μA with 50MHz main clock frequency, which is less than 33 % of other reports. The frame rate of the proposed CMOS Image Sensors (CIS) is maximum 35 fps. The proposed circuit has a redundancy error correction logic for to calibrate error between coarse and fine conversions. Total power consumption 28 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital).