A 0.8 to 1.3 GHz ADPLL Design using a Mismatching Parallel TDC
0.8~1.3 GHz 대역의 불일치 병렬 TDC를 이용한 ADPLL설계
- 주제(키워드) PLL , ADPLL , TDC
- 발행기관 서강대학교 일반대학원
- 지도교수 범진욱
- 발행년도 2019
- 학위수여년월 2019. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/sogang/000000063774
- UCI I804:11029-000000063774
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권보호를 받습니다.
초록/요약
This work proposes a 0.8 to 1.2 GHz All-Digital Phase-Locked Loop (ADPLL) with low-jitter performance using 2-step time-to-digital converter(TDC) including a mismatching parallel TDC without delay line. The proposed 2-step TDC consists of a bang-bang phase detector(BBPD), a phase shifter, a mismatching parallel TDC and a low-resolution TDC. A mismatching parallel TDC improves accumulated jitter by remove delay line, and a low-resolution TDC makes up the disadvantage of a BBPD causing nonlinear of phase detector gain and slow acquisition time. By using the phase shifter, the proposed architecture can detect bi-direction signal and achieve low power consumption and small occupied area. The proposed ADPLL has been implemented in Magna-chip 0.18㎛ CMOS technology. This ADPLL has locking point at 1GHz and external reference frequency is 31.25MHz. The area of core is 0.59 and the total power consumption of the ADPLL is 9.72mW under 1.8V supply voltage at locking.
more