서강대학교

초록/요약

With vast IP traffic to be forwarded, system failure is critical to routers. Should such occur in practice, the system is reset, and components undergo a short period of power loss. The drawback of this measure is that data stored in volatile memories is lost. This is a problem, as conventional routers store their forwarding tables in DRAM. While phase change memory(PCM) is an emerging alternative for DRAM, its high read/write latency stands in the way of being an immediate replacement. This thesis seeks to design a high performance standalone PCM-based memory system for IP lookup, by making three major modifications to the conventional PCM architecture. The key idea is to read just enough data from PCM cells for low latency and make full advantage of numerous existing banks within the system. First, I propose fast-visit, where only half the node is read for low latency when visiting intermediary trie nodes on conducting a lookup. Second, I propose a duplicate-driven memory system, where an incoming request is scheduled to the system-transparent duplicate of highest availability. Third, I propose a modified buffer layout that supports shared inter-bank buffers, to better utilize multiple buffers at PCM banks. Performance evaluation shows an average of 10.6% bandwidth improvement over the DRAM baseline system, and an 83.4% over the PCM baseline.