서강대학교

초록/요약

Recently, the power consumption of the processors used in mobile devices has been emphasized. Most mobile devices are battery operated; thus, batteries are required to be available for a long time once charged. For this, increasing the capacity of the battery is the easiest way, but this is not the right approach because there is a limit to the size and weight to carry. Therefore, studies are under way to reduce battery consumption (i.e., power consumption). However, since power consumption and performance are in a trade-off relationship, it is inadvisable to reduce only the power consumption. In particular, the performance of microprocessors has evolved rapidly, while the performance of memory inside the processor has not improved significantly. Because memory is a device included in the processor, improving memory performance can lead to processor performance improvement. In order to improve the performance of the memory, it is desired to improve the performance of the cache memory existing between the CPU and the main memory. Therefore, this paper proposes a new cache specification considering both power consumption and performance of the processor in mobile devices. In this study, the performance of both memory and processor was enhanced and the power consumption was reduced by finding proper cache specification considering both power consumption and performance in the trade-off relation. ARM Cortex-A57 was chosen as the target AP for the simulation. Performance measurements were performed with SimpleScalar 3.0 and power consumption measurements were performed with McPAT 1.0. The performance, power consumption, and area of the proposed cache specification were compared with those of the conventional cache specification. As a result, the total area of the processor was reduced by 3.44%, and the total peak power decreased by 0.66% and the runtime dynamic power by 2.81 reflecting the actual benchmark results. Performance increased by 0.19% for CPI and 0.34% for AMAT, which could be solved by increasing the core clock frequency as much as reduced power of the processor. The core clock frequency of the conventional Cortex-A57 is 2000MHz, which can be used up to 2040MHz based on total peak power and up to 2070MHz based on runtime dynamic power. Thus, using up to 2070 MHz results in 3.2% reduction in CPI and 3.1% reduction in AMAT, compared to using the conventional cache specification. In other words, faster operation means the improvement of the performance of the processor. In conclusion, applying the proposed cache specification to the target AP, Cortex-A57, can reduce power consumption while improving performance. Although this study considers both performance and power consumption in a trade-off relationship in a mobile processor, it is significant in that it provides a result and direction that can benefit both sides by changing only the cache specification.