A 12 bit Two-step SAR ADC for High-Speed CMOS Image Sensor Applications
- 발행기관 서강대학교 일반대학원
- 지도교수 범진욱
- 발행년도 2018
- 학위수여년월 2018. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/sogang/000000062777
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권보호를 받습니다.
초록/요약
A 12bit 250 kS/s CMOS a successive approximation register Analog to digital converter (SAR ADC) for voltage domain sensor application is presented in this thesis. The SAR ADC has trade-off between size and high resolution specification. The capacitor array in high resolution SAR ADC has size problem because total capacitance of capacitor array increase exponentially as the ADC resolution increase. To overcome this issue, the proposed SAR ADC is used the resistor array with the capacitor array. Also the proposed SAR ADC applied addition-only digital error correction(ADEC) algorithm. The ADEC algorithm has the redundant decision cycles between the capacitor DAC with the resistor DAC. A prototype ADC was implemented in a 90-nm CMOS technology. The chip consumes 145 μW under a 2.8-V supply. The ADC core occupies an active area of 0.011mm × 0.95mm.
more