서강대학교

초록/요약

This thesis proposes a 30 MHz analog controlled voltage-mode buck converter and a 4 MHz digitally controlled voltage-mode buck converter using delay-line-based control techniques. The 30 MHz analog controlled voltage-mode buck converter is controlled by a delay-line-based pulse-width-modulation (PWM) controller to regulate its output voltage. Also, two voltage-to-delay cells are used to convert the voltage difference to delay-time difference. A charge pump is used to charge or discharge a loop filter, depending on whether the feedback voltage is larger or smaller than the reference voltage. A delay-line-based voltage-to-duty-cycle (V2D) controller is used to replace the classical ramp-comparator-based V2D controller to accommodate wide duty cycle variations. A type-II compensator is implemented in this design with a capacitor and resistor in the loop filter. The prototype buck converter was fabricated using a 0.18-μm CMOS process. It occupies an active area of 0.834 mm2 including the testing pads. The tunable duty cycle ranges from 11.9% to 86.3%, corresponding to 0.4 V to 2.8 V output voltages, respectively, with 3.3 V input. With a step of 400 mA in the load current, the settling time is around 3 μs. The peak efficiency is as high as 90.2% with 450 mA load current at 2.4 V output voltage. The maximum measured load current is 800 mA. In the 4 MHz digitally controlled voltage-mode buck converter, two voltage delay controlled lines are used to convert the feedback and reference voltage difference to time delay difference before entering a multiple outputs bang-bang phase detector (MOBBPD), which can converter the time delay difference to multiple digital codes in a simple way. After that, the digital loop filter (DLF) can accumulate the digital codes to control the duty cycle of digital pulse width modulator (DPWM) for regulating the output voltage. By adjusting the coefficients of DLF, a type-II compensator can be achieved through the integral and proportional paths to make the loop stable. The novel DPWM consists of a divide-by-8 frequency divider, two delay lines, and simple digital control logic, which can achieve a wide tunable range of duty cycle under different corners and supply voltages. The measured results show that the buck converter has a very wide output voltage ranging from 0.1 V to 3.5 V and input voltage ranging from 2.4 V to 3.6 V. With a 400 mA step in the load current, the overshoot/undershoot is less than 87 mV and the 1% settling time is less than 16 μs. The peak efficiency is 95.2% with 250 mA load current at 2.4 V output voltage with 3.3 V input voltage. The prototype of proposed buck converter was fabricated in 0.18-μm CMOS technology.