서강대학교

초록/요약

A 12bit 500 kS/s CMOS a successive approximation register Analog-to-digital converter (SAR ADC) for voltage domain sensor application is presented in this paper. A sensor which is based on voltage-domain has many issues in high resolution and low power. In this application, the SAR ADC is the most power efficient model in overall ADC. The SAR ADC also has trade-off between size and high resolution specification. The capacitor array in high resolution SAR ADC has size problem because total capacitance of capacitor array increase exponentially as the ADC resolution increase. To overcome this issue, the proposed SAR ADC is used top-plate sampling which can half of total capacitance than conventional one. Also the proposed SAR ADC applied 2 types of technique which can consume lower switching power. The first technique is a charge recycling switch to reduce capacitor array switching power consumption. The second technique which is Most significant bits (MSB) split capacitor array can reduce MSB settling time to enhance of overall ADC speed. The SAR ADC is designed using a 0.18 μm CMOS process. At a 1.8-V supply voltage and a 500 KS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 60.08dB and consumes 60.58 μW. The ADC core occupies an active area of 0.341 mm2.