A Time-Interleaved and Circuit-Shared Dual-Channel 10b 200MS/s 0.18um CMOS ADC
- 발행기관 서강대학교 일반대학원
- 지도교수 이승훈
- 발행년도 2013
- 학위수여년월 2013. 2
- 학위명 석사
- 학과 및 전공 일반대학원 전자공학과
- 실제URI http://www.dcollection.net/handler/sogang/000000049328
- 본문언어 영어
- 저작권 서강대학교 논문은 저작권 보호를 받습니다.
초록/요약
This work proposes a 10b 200MS/s pipeline ADC for high-quality video systems based on double-channel and op-amp sharing schemes to minimize power consumption and channel mismatch. The double-channel time-interleaved scheme reduces the required operating speed of amplifiers in the SHA and MDACs by 50%. The switched and shared op-amp with two input pairs amplifies each channel signal without extra series switches while minimizing the gain, bandwidth, and offset mismatches between channels. The low-jitter sampling clock with a 50% duty cycle improves the dynamic performance of the wideband input signals significantly. The flash ADCs employ a DDA type pre-amp to continuously process dual-channel outputs. The prototype ADC in a 0.18um CMOS technology demonstrates the measured DNL and INL within 0.62LSB and 0.99LSB, respectively. At 200MS/s, the ADC shows a maximum SNDR of 52.8dB and a maximum SFDR of 60.4dB. The ADC with an active die area of 1.28mm2 consumes 54.0mW at 1.8V.
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