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A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC Using a Range-Scaling Scheme


This work proposes a 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC optimizing power consumption and chip area for various IP applications. The proposed DAC employs a 2-step (6b-4b) split-capacitor array with the VCM-based switching method and two unit capacitors in series to act as a minimum unit capacitor for high power efficiency and small chip area. Additionally, a range-scaling technique is employed for a rail-to-rail input signal swing. The comparator accuracy is improved by offset cancellation techniques in the first-stage pre-amp. The digital blocks, such as the SAR logic and control logic, are optimized additional low-powr dissipation and smaill chip area. The noise due to a disturbance of power supply is reduced by implementing the proposed ADC as a fully differential circuit structure, even if dealing with single-ended input signals. The prototype ADC in a 0.11um CMOS technology demonstrates the measured DNL and INL within 1.07LSB and 1.66LSB at 10b, respectively. The ADC shows a maximum SNDR of 54.4dB and a maximum SFDR of 69.8dB at 10MS/s, respectively. The ADC with an active die area of 0.25mm2 consumes 2.3mW at a 1.2V and 10MS/s.