서강대학교

초록/요약

This thesis proposes low-voltage 12b 160MS/s and 10b 120MS/s pipeline analog-to-digital converters (ADCs) in advanced CMOS technologies. A 12b 1.2V 160MS/s ADC for high-definition video systems is presented. The proposed multipath frequency-compensation technique enables the conventional reversed nested Miller compensation (RNMC)-based three-stage amplifier to achieve a stable operation at a sampling rate of 160MS/s. The measured differential non-linearity (DNL) and integral non-linearity (INL) of the prototype ADC implemented in a 65nm CMOS process are less than 0.69LSB and 1.00LSB respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio (SNDR) of 58.5dB and 53.1dB and a maximum spurious-free dynamic range (SFDR) of 76.0dB and 67.8dB at 160MS/s and 200MS/s, respectively. The ADC with an active die area of 0.72mm2 shows a figure of merit of 0.75pJ/conversion-step at 160MS/s and 1.2V. A 10b 120MS/s pipeline ADC is implemented in a 45nm CMOS process. Three-stage amplifiers based on RNMC and Multipath zero cancellation techniques are employed in the input sample-and-hold amplifier (SHA) and two multiplying digital-to-analog converters (MDACs). A single re-configurable three-stage switched amplifier is shared between two adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs. A charge redistributed input sampling network properly handles both single-ended and differential SHA inputs with a swing range of 1.2Vpp around a 1.6V common-mode voltage. The prototype ADC with an active die area of 0.58mm2 consumes 61.6mW at 120MS/s and 1.1V. The measured DNL and INL are ess than 0.44LSB and 0.75LSB, respectively. At a sampling rate of 120MHz with a 4.2MHz sinusoidal input, the measured maximum SNDR and SFDR are 55.6dB and 70.4dB, respectively.