서강대학교

초록/요약

This paper proposes two essential IPs of a 12b and 14b 50MS/s analog-to-digital converters (ADCs) for high-quality display systems such as ultrasound vision systems, charge coupled devices, computed tomography scanners, and portable communication terminals, respectively. A 12b 50MS/s 0.18um CMOS pipeline ADC is proposed. The proposed capacitor and operational amplifier (op-amp) sharing techniques merge the front-end sample-and-hold amplifier (SHA) and the first multiplying digital-to-analog converter (MDAC1) to achieve low power without an additional reset timing and a memory effect. The second and third MDACs share a single op-amp to reduce power consumption further. A shared op-amp of the merged SHA and MDAC1 controls properly the input trans-conductance for stability at each clock phase of holding and amplifying. The prototype ADC in a 0.18um CMOS process demonstrates the measured differential non-linearity (DNL) and integral non-linearity (INL) within 0.53LSB and 2.09LSB, respectively. The ADC shows a maximum signal-to- noise-and-distortion (SNDR) ratio of 60.6dB and a maximum spurious-free dynamic range (SFDR) of 69.4dB at 50MS/s. The ADC with an active die area of 0.93mm2 consumes 21.6mW at 50MS/s and 1.8V. The proposed 14b 50MS/s 0.18um CMOS 4-stage pipeline ADC based on a digital code-error calibration. The proposed calibration technique measures the capacitor mismatch errors of the front-end MDAC with the back-end pipeline stages while the measured code errors are stored in memory and corrected in the digital domain during normal conversion. The calibration needs the increased power dissipation and chip area of 1.4% and 10.7%, respectively, compared to a 14b un-calibrated conventional pipeline ADC. The prototype ADC fabricated in a 0.18um CMOS process occupies an active die area of 4.2mm2 and consumes 140mW at 1.8V and 50MS/s. After calibration, the measured DNL and INL of the ADC are improved from 0.69LSB to 0.39LSB and from 33.60LSB to 2.76LSB, respectively.