서강대학교

초록/요약

As technology progresses to nano-scale, the effect of process variation is no more ignorable. Timing problems such as meeting timing, clock period are challenged by the process variation. A delay of circuit forms no more deterministic value. It transforms as delay distribution, so new modeling and propagation methods are researched. In addition, the yield estimation and optimization through the delay distribution is extensively researched. However, these researches are done under gate level or transistor level. It is need to take the effect of process variation into the high-level synthesis stage. Conventional high-level synthesis used the delay of functional unit as a worst case based deterministic value. The corner based approach does not consider the yield, so it is impossible to estimate the yield of the result. To make matters worse, the result of synthesis is too pessimistic like requires more than necessary resources. This thesis proposes variation-aware force-directed scheduling for high-level synthesis that uses the delay distribution of functional unit which can be obtained by statistical static timing analysis. The proposed algorithm can estimates the yield of synthesis and tries to minimize resource requirement. Experimental results on benchmark circuits show that the proposed algorithm can effectively reduce the resource requirement with preserving the performance.