Cost-Effective 12-bit High-Speed ADCs for Video Applications : 1.2V 12b 120MS/s SHA-Free Dual-Channel Nyquist ADC Based on Mid-Code Calibration, 12b 50MS/s CMOS Nyquist ADC with a Fully Differential Class-AB Switched OP-AMP
- 발행기관 서강대학교 전자공학과 대학원
- 지도교수 이승훈
- 발행년도 2009
- 학위수여년월 2009. 2
- 학위명 박사
- 실제URI http://www.dcollection.net/handler/sogang/000000044886
- 본문언어 영어
초록/요약
This work proposes two precious IPs: a 12b 120MS/s dual-channel pipeline analog-to-digital converter (ADC) and a 12b 50MS/s pipelined CMOS ADC for video signal processing systems. A 12b 120MS/s dual-channel pipeline ADC is proposed for high-speed video signal processing. A simple digital mid-code calibration technique is proposed to eliminate offset mismatches between channels. The proposed SHA-free architecture with correlated input sampling networks enables wideband signal sampling while effectively reducing a gain mismatch between channels. The prototype ADC implemented in a 0.13um CMOS technology achieves a peak signal-to-noise-and-distortion ratio of 61.1dB and a peak spurious-free dynamic range of 74.7dB for input frequencies up to 60MHz at 120MS/s. The measured differential and integral nonlinearities are within 0.30LSB and 0.95LSB, respectively. The ADC occupies an active die area of 0.56mm2 and consumes 51.6mW at 1.2V power supply. The proposed 12b 50MS/s pipelined CMOS ADC based on a fully differential class-AB switched op-amp exhibits low power consumption with a high differential input range of 2.4Vp-p. The attenuated dynamic common-mode feedback (CMFB) circuit is proposed to enable the fully differential operation in clock based system. The proposed SHA-free input sampling network, composed of only gate-bootstrapping switches and sampling capacitors, samples high-swing wideband signals exceeding the Nyquist frequency. The proposed current generator insensitive to PVT variations is integrated on chip for stable operation within the temperature range of -55℃ to 125℃ at the wide supply voltage from 1.5V to 2.2V. The prototype ADC achieves a peak SNDR of 64.0dB and a peak SFDR of 76.6dB for a 2.4Vp-p and 31MHz input signal at 50MS/s, while the measured DNL and INL are within 0.26 LSB and 0.72 LSB, respectively. The prototype ADC in a 0.18m 1P6M CMOS process shows a power dissipation of 18.4mW at 50MS/s and 1.8V with an active die area of 0.26mm2.
more목차
1. Cost-Effective and High-Performance ADCs for Video Applications = 1
2. 12b 120MS/s Dual-Channel ADC for Didigtal TV = 4
2.1 Introduction = 4
2.2 Dual-Channel ADC Architecture and Calibration = 9
2.2.1 Dual-Channel ADC Architecture = 9
2.2.2 Mid-Code Calibration = 14
2.3 Dial-Channel ADC Circuit Implementation = 18
2.3.1 Input Sampling Network = 20
2.3.2 Resistor Free Comparator = 26
2.3.3 Two-stage Switched Op-amp = 30
2.4 Dual-Channel ADC Implementation and Measurements = 33
3. 12b 50MS/s Low-Power ADC for Mobile TV = 45
3.1 Introduction = 45
3.2 ADC Architecture and Circuit Implementation = 47
3.2.1 ADC Architecture = 47
3.2.2 Fully Differential Class-AB Op-amp = 49
3.2.3 Bias Voltage Generator = 52
3.3 Prototype ADC Measurements = 56
4. Conclusion = 64
References = 67
List of Figures
Fig 1 Forecast of global semiconductor market = 2
Fig 2 Block diagram of a time-interleaved ADC architecture = 7
Fig 3 Block diagram of the proposed dual-channel ADC = 11
Fig 4 Single-channel ADC architecture of Fig 3 = 13
Fig 5 Functional description of a mid-code digital calibration: (a) Before calibration and (b) After calibration = 17
Fig 6 Simplified input sampling network based on MDAC1 and FLASH1 = 21
Fig 7 Simulated conditions of input frequency, sampling time mismatch, and comparator offsets for no-missing code: (a) Based on MDAC1 with no offset and (b) Based on MDAC1 with an offset voltage of 15mV = 25
Fig 8 Coding technique of the proposed ADC = 27
Fig 9 FLASH architecture: (a) Capacitor-divided latched comparator and (b) Proposed 2.5b FLASH scheme = 29
Fig 10 Two-stage switched op-amp for MDAC1 = 32
Fig 11 Die micrograph of the proposed dual-channel ADC = 34
Fig 12 Measured DNL and INL of each ADC channel: (a) A Channel and (b) B Channel = 36
Fig 13 Measured DNL and INL of the proposed dual-channel ADC: (a) Before calibration and (b) After calibration = 37
Fig 14 Measured FFT spectrums of each ADC channel (fck = 60MHz, fin= 59.9MHz): (a) A Channel and (b) B Channe = 39
Fig 15 Measured FFT spectrums of the proposed dual-channel ADC(fck = 2×60MHz, fin = 59.9MHz): (a) Before calibration and (b) After calibration = 40
Fig 16 Measured SNDR and SFDR = 42
Fig 17 Proposed ADC and input sampling network = 48
Fig 18 Proposed fully differential class-AB switched op-amp = 50
Fig 19 Proposed PVT-insensitive bias generator = 53
Fig 20 Die photo of the proposed ADC = 57
Fig 21 Measured DNL and INL = 59
Fig 22 Measured FFT plot (fIN = 31MHz and fS = 50MHz) = 60
Fig 23 Measured SFDR and SNDR (fIN = 4MHz) = 62
Fig 24 FoM of 12b ADCs = 66
List of Tables
Table 1 Performance summary of the Proposed Dual-Channel ADC = 44
Table 2 Performance summary of the prototype 12b 50MHz ADC = 63
