Implementation and design of CMOS Direct-conversion Transmitter IC for WLAN/WMAN 5GHz band
- 주제(키워드) RFIC , CMOS transmitter , WLAN , WMAN
- 발행기관 서강대학교 대학원
- 지도교수 범진욱
- 발행년도 2009
- 학위수여년월 2009. 2
- 학위명 박사
- 실제URI http://www.dcollection.net/handler/sogang/000000044843
- 본문언어 영어
초록/요약
As CMOS technologies has grown, CMOS IC markets have also been expanding to new areas, wireless communication system. High throughput WLAN markets such as 802.11x family already had started, attention is also being focused on longer distance system such as WMAN and WiBro. CMOS down-scaling helps to increase the maximum cut-off frequency, which provides superior performance for RF characteristics such as low noise, oscillation frequency, and available gain. However, the down-scaling of CMOS has deteriorated its high power handling capability, directly relevant to its linearity, which is an important factor for RF transmitter. Additionally, the CMOS transmitter ICs have relatively less studied than CMOS receivers. Hence, this thesis focuses on the implementation of CMOS RF transmitter and the improvement of non-linearity on low voltage supply. To increase the linear properties such as 1 dB compression point, new up-converter architecture is proposed and implemented on a 0.18 CMOS technology. To prevent voltage clipping that leads to a power compression from low supply voltage, V-I converters were used at the mixer input stage and 4 multiple paths were used with 4 different phases (0˚, 90˚, 180˚, and 270˚) at the output. The mixers behaved as both phase shifter and frequency up-converter so that the 4 multiple path structure with different phases can be integrated readily without large passive phase-shifters. The 4 multiple path provided not only the increase of the output power capability but the reduction of an LO (Local Oscillator) leakage. Simultaneous power combining and leakage cancellation technique is firstly proposed in this study. The fabricated up-converter showed significantly high input a P1dB of 0 dBm, 7.3 dB additional LO leakage cancellation, and a conversion gain of 6 dB from 1.8 V supply.
more초록/요약
CMOS 공정 기술이 발전함에 따라 CMOS IC 시장은 무선 통신이라는 새로운 시장으로 그 영역을 넓혀가게 되었다. 802.11x 같은 고속 통신용 WLAN 시장은 이미 열려 있고, 점차 WMAN과 WiBro 같은 원거리 고속 통신이 주목받고 있다. CMOS down-scaling은 maximum cut-off frequency를 증가시키고, 이는 low noise, oscillation frequency, gain이 중요한 RF 특성을 높이는 데 도움을 준다. 그러나 CMOS의 down-scaling은 높은 파워 구동 능력 (선형성과도 직접적으로 연관성이 있음)을 떨어뜨리는 문제가 있어 transmitter 설계에는 방해요인이 된다. 게다가 CMOS transmitter IC는 상대적으로 receiver와 비교하면 발표된 논문의 수가 빈약하다. 이러한 연유로 본 논문은 RF transmitter의 구현과 저전압에서의 비선형성을 증가시키는 방법에 대해서 연구하게 되었다. 1 dB compression point로 대표되는 선형적 특성을 증가시키기 위해서, 새로운 up-converter 구현방법을 제안하였으며, 0.18um CMOS로 이를 구현하였다. 저전압 때문에 발생하는 파워 compression에 의한 voltage clipping을 막고자, V-I converter를 mixer의 입력단에 채용하였으며, 4가지의 phase를 가지는 4개의 path를 병렬로 연결하여 선형성을 증가시켰다. 제안한 구조에서 mixer는 phase shifter와 frequency up-conversion을 동시에 수행하게 되며, 4개의 multiple path structure는 큰 면적을 차지하는 passive phase-shifter 없이 쉽게 구현이 가능해졌다. 그 4 multiple path는 출력 파워의 증가뿐만 아니라 LO leakage의 줄이는 방법도 제공하게 되며, Power combine과 leakage cancellation을 동시에 구현하는 이 방법은 본 연구에서 처음으로 제안되었다. 제작된 up-converter는 1.8 V의 저전압에서 6 dB의 conversion gain과 월등히 증가한 0 dBm의 입력 P1dB를 가졌으며, 7.3 dB의 추가적인 LO cancel이 측정되었다.
more목차
Chapter 1 Introduction = 1
Chapter 2 Fundamentals of 5 GHz RF front-end system = 3
2.1 WMAN/WLAN (IEEE 802.16a, 11a) overview = 3
2.1.1 OFDM = 5
2.1.2 Advances in CMOS RFIC technology = 8
2.2 RF transmitter architecture = 12
2.2.1 Heterodyne ( or super-heterodyne) transmitter = 14
2.2.2 Direct conversion transmitter = 15
2.2.3 VCO push/pulling = 17
2.2.4 Phase/gain mismatch (I/Q mismatch) = 19
2.2.5 Carrier leakage = 20
Chapter 3 RFIC sub-block design = 22
3.1 RF transmitter circuit design fundamentals = 22
3.1.1 Linearity analysis = 22
3.1.2 New simple and intuitional linear analysis method in time-domain = 24
3.1.3 P1dB due to voltage clipping = 24
3.1.4 P1dB - voltage headroom relation in differential structure = 30
3.1.5 Design to improve linearity of the Up-converter = 33
3.2 Power amplifier = 37
3.2.1 An overview of power amplifier = 37
3.2.2 A linear or nonlinear Power amplifiers = 38
3.2.2.1 Class A or AB = 39
3.2.2.2 Class B = 40
3.2.3 Design and implementation of RF amplifier = 41
3.2.3.1 Stability = 41
3.2.3.2 Inter-stage matching = 42
3.2.4 Implementation = 44
3.3 Mixer = 50
3.3.1 Design of the high P1dB sub-harmonic Tx mixer = 50
3.3.2 Results of mixer = 55
3.4. LO generator = 57
3.4.1 An overview of LO generator = 57
3.4.2 VCO(Voltage Control Oscillator) = 60
3.4.2.1 Phase noise = 60
3.4.2.2 Phase noise in VCO = 62
3.4.3 Design Techniques To Reduce Phase Noise = 65
3.4.4 Implementation of VCO = 66
3.4.4.1 8-phases VCO design = 66
3.4.5 Results of VCO = 71
3.5 Periphery circuits for transmitters = 78
3.5.1 Down-mixer for a calibration = 78
3.5.2 RF CMOS switch = 79
Chapter 4 The Implementation of WMAN/WLAN (IEEE 802.16a, 11a) dual - band transmitter = 81
4.1 WMAN/WLAN dual-band transmitter system design = 81
4.1.1 Link budget design = 81
4.1.2 Results = 83
4.1.3 I/Q mismatch calibration = 86
4.2 Transmitter architecture with power combine and LO leakage cancellation = 88
4.2.1 Conventional power combine = 88
4.2.2 Proposed up-converter with power combine and LO cancellation = 92
Chapter 5 Discussion = 98
5.1 Conventional power combination method = 98
5.2 The proposed power combination method = 100
Chapter 6 Conclusion = 104
REFERENCE = 106
List of Tables
Table 1. The detectable range of a receiver according to Tx. power = 13
Table 2. The comparison between direct-conversion and traditional heterodyne architectures = 16
Table 3. Properties of a power amplifier accordingly to its class = 39
Table 4. Comparison of simulation and measured data = 55
Table 5. Comparison simulation with measurement phase noise = 74
Table 6. Comparison the proposed switch and the others = 80
Table 7. A performance comparison of reported up-converters = 102
List of Figures
Fig. 1 OFDM spectrum of 802.11a in frequency domain = 4
Fig. 2 Multi sub-carrier division multiplex = 5
Fig. 3 Simple OFDM modulation/demodulation procedures = 6
Fig. 4 Transmitter and receiver structures of IEEE 802.11a = 7
Fig. 5 802.16 OFDM frequency description = 8
Fig. 6 Major RF performance factors according to CMOS process scaling at 2 GHz. = 10
Fig. 7 Bond wires in Micro-lead frame package = 11
Fig. 8 Transmitted spectrum must comply with the corresponding Tx. mask. = 12
Fig. 9 Heterodyne transmitter architecture = 14
Fig. 10 Direct conversion transmitter architecture = 15
Fig. 11 Oscillator pulling in RF transmitter = 17
Fig. 12 Injection pulling as the magnitude of the injected noise increases. = 17
Fig. 13 (a) feedback oscillator (b) LCR load, β(s) (c) Injection of current at the load (d) frequency shift by injection = 18
Fig. 14 Gain/phase imbalance due to IQ mismatch = 20
Fig. 15 conventional cascode topology = 25
Fig. 16 voltage swing when clipping at output node due to headroom = 25
Fig. 17 Power characteristics of clipping and non-clipping signal = 27
Fig. 18 The clipped signal (= periodic function) and 5th-order fourier series (N=5) = 28
Fig. 19 voltage clipping due to voltage headroom = 30
Fig. 20 Comparison results of harmonic-balance simulator and the proposed hand-calculation for a differential drive amplifier. = 31
Fig. 21 (a) single-ended common source structure (b) differential-ended or = 35
Fig. 22 spectral re-growth of nonlinear PA = 38
Fig. 23 A linear two-port network = 42
Fig. 24 design of the load considering interstage-matching = 43
Fig. 25 Smith chart = 43
Fig. 26 A cascode and resistive feedback topology for RF amplifier. = 44
Fig. 27 Die photograph of the designed power amplifier = 45
Fig. 28 Test bench of the differential power amplifier for 2-port analysis = 46
Fig. 29 (a) Photo of a mounted Murata 5 GHz balun on PCB (b) phase and gain difference over wide frequency. = 47
Fig. 30 Loss of balun due to phase mismatch. = 47
Fig. 31 Measurement setup for differential power amplifier = 48
Fig. 32 NMOS size W=200 ？玧？, L=0.18 ？玧？ (a) RF output power over input power when gate and cascode bias voltage as 0.8 / 2.15 V, respectively (b) when 0.6 /2.85 V = 49
Fig. 33 The proposed high P1dB sub-harmonic mixer = 50
Fig. 34 (a) An operation of the conventional Gilbert mixer and = 51
Fig. 35 The embedded V-I converter in the mixer input stage = 52
Fig. 36 Total output current, iout, is the combination of iout+ and iout- of input V-I converter. (a) I-V characteristics of the V-I converter (b) The second derivative of the trans-conductance = 54
Fig. 37 Simulation results in output P1dB = 1.6 dBm (X - input power, Y- output power in dBm) = 56
Fig. 38 Measured data output P1dB = -1 dBm = 56
Fig. 39 Frequency synthesizer in RF transmitter = 57
Fig. 40 PLL as a negative feedback model = 58
Fig. 41 Leeson's phase noise model = 62
Fig. 42 Model of L-C oscillator = 63
Fig. 43 LO-signal generation for sub-harmonic mixer = 66
Fig. 44 The block diagram of 8-phase VCO = 67
Fig. 45 The schematics of identical VCO cells = 68
Fig. 46 Schematics of the a) P-QVCO, b) TS-QVCO, and c) BS-QVCO = 69
Fig. 47 Layout of the quadratue-VCO = 71
Fig. 48 Simulation of phase noise; (i) -96.1 dBc/Hz @ 100 kHz (ii) -124 dBc/Hz @ 1 MHz offset frequency = 71
Fig. 49 The output swing of ring-oscillator type quadrature LC-VCO; each VCO emits 45° phase shifted LO. = 72
Fig. 50 Measured phase noise of LC-VCO = 73
Fig. 51 Magnitude of the generated LO fundamental and the second harmonic = 73
Fig. 52 The measured frequency, output power, and dissipated DC power of the quadrature-VCO with buffers ( SW = 0, 0) = 75
Fig. 53 The measured frequency, output power, and dissipated DC power of the quadrature-VCO with buffers ( SW = 1, 0) = 75
Fig. 54 The measured frequency, output power, and dissipated DC power of the quadrature-VCO with buffers ( SW = 0, 1) = 76
Fig. 55 The measured frequency, output power, and dissipated DC power of the quadrature-VCO with buffers ( SW = 1, 1) = 76
Fig. 56 The measured frequency range with band selection (SW = 00, 01, 10, 11) = 77
Fig. 57 Schematic of down mixer (sub-harmonic) for calibration = 78
Fig. 58 Power characteristics of the calibration mixer, input vs. output power = 79
Fig. 59 The proposed RF CMOS switch enhanced by AC ground = 79
Fig. 60 Design result of the transmitter link budget, the table beneath refers to commercial products used in designing budget. = 81
Fig. 61 Instant power vs. mean of power on time domain of OFDM = 82
Fig. 62 BER degradation due to non-linearity of power amplifier = 82
Fig. 63 simplified transmitter block diagram = 83
Fig. 64 Measured data of power characteristics (the third harmonic and fundamental output power) = 84
Fig. 65 spectrum of output power when output power emits 24.8 dBm = 84
Fig. 66 Transmitter diagram with I/Q calibration path = 86
Fig. 67 A part of calibration path in detail = 86
Fig. 68 Front-end amplifier of transmitters = 88
Fig. 69 The process power combine of the 180° differential signal through balun = 89
Fig. 70 Increasing output power using a 4 parallel power combine = 90
Fig. 71 The input P1dB simulation result of a power amplifier and their power combine structure = 91
Fig. 72 Simplified schematic of the proposed up-converter architecture = 93
Fig. 73 (a) A simplified block diagram of the proposed sub-harmonic architecture with a viewpoint of combining the signal (b) A simplified block diagram with a viewpoint of LO leakage cancellation = 95
Fig. 74 (a) A simplified schematic of the sub-harmonic mixer (b) A simplified schematic of a part of the sub-harmonic mixer to explain how LO leakage generates, and the numbers mean a sequence of the LO leakage generation. = 96
Fig. 75 Structure of DAT = 98
Fig. 76 Gain and PAE versus output power = 99
Fig. 77 the simplified proposed power combination method = 100
Fig. 78 Measured by oscilloscope at node A and B when sine wave was injected as input. = 100
Fig. 79 Signal to LO leakage ratio of (a) conventional (b) proposed transmitter = 101
