A Implementation of Fully Integrated Frequency synthesizer For ISM Band Transceivers
- 발행기관 서강대학교
- 지도교수 범진욱
- 발행년도 2009
- 학위수여년월 2009. 2
- 학위명 석사
- 실제URI http://www.dcollection.net/handler/sogang/000000044834
- 본문언어 영어
초록/요약
A fully integrated frequency synthesizer for the ISM radio band transceivers has to exhibit very low phase noise characteristic and very small chip size. Phase noise of frequency synthesizer is the crucial parameter which is the criterion of ISM radio band transceivers. The chip size of frequency synthesizer is related to the cost of ISM radio band transceivers. The proposed frequency synthesizer in this paper has 450MHz center frequency and -131dBc/Hz phase noise at 1MHz offset. LC-VCO that determines phase noise of the frequency synthesizer is precisely predicted with well known phase noise model. The phase noise of LC-VCO is minimized by maximizing quality factor of LC-VCO. The new charge pump which adopted in frequency synthesizer is proposed to reduce non-ideal characteristics of conventional charge pump. The proposed charge pump improves non-ideal factor more than 80% better than conventional charge pump. The jitter of frequency synthesizer with the conventional charge pump and the proposed one is predicted to be 2.37ns and 1.5ns, respectively. If designed LC-VCO and proposed charge pump adopted in frequency synthesizer for ISM radio band transceiver, it will exhibit better performance than the other ISM radio band transceivers. The designed circuits have been implemented with 0.18㎛ CMOS technology.
more초록/요약
ISM대역용 송수신기를 위한 집적화된 주파수 합성기는 아주 낮은 위상잡음특성과 아주 작은 칩 사이즈의 특성을 가져야 한다. 주파수합성기의 위상잡음특성은 대역용 송수신기의 특성을 결정짓는 중요한 파라미터이다. 그리고 주파수 합성기의 칩 사이즈는 ISM 대역용 송수신기의 단가와 관련이 되어 있다. 본 논문에서 제안된 주파수 합성기는 중심주파수 450MHz, 위상잡음특성-131dBc/Hz@1MHz offset의 특성을 가졌다. 주파수 합성기의 위상잡음특성을 결정짓는 LC-전압제어발진기는 정확한 예측을 위해 위상잡음특성 모델링을 이용하여 설계되었고, LC-전압제어발진기의 양질계수의 값을 최대화함으로써 위상잡음특성을 최소화하였다. 제안된 주파수 합성기는 전하펌프의 비이상적인 특성을 최소화 하고자 성능이 향상된 전하펌프가 제안되었다. 제안된 전하펌프는 기존의 전하펌프의 문제점을 80%이상 개선하였다. 제안된 전하펌프가 적용된 주파수 합성기의 지터는 1.5ns로 예상되었고, 기존 전하펌프의 경우 2.37ns로 예상되었다. 설계된 LC-전압제어발진기와 제안된 전하펌프가 적용된 주파수 합성기는 ISM대역용 송수신기 적용될 경우 기존의 송수신기보다 뛰어난 특성의 송수신기로 계발 될 것이다. 설계된 모든 회로는 0.18 m CMOS 공정으로 설계되었다.
more목차
Chapter 1. Introduction = 1
Chapter 2. Analysis and implementation of LC-VCO = 3
2.1 Integrated inductor = 3
2.2 Integrated varactor = 6
2.3 Integrated inductor and varactor based VCO = 7
Chapter 3. Proposed charge pump = 9
3.1 Conventional charge pump = 9
3.2 Proposed charge pump = 12
Chapter 4. Frequency synthesizer structure = 17
4.1 Fractional-N frequency synthesizer structure = 17
4.2 Sigma-delta modulator = 20
4.3 Third-order loop filter = 24
4.4 Phase Frequency Detector(PFD) = 27
Chapter 5. Simulated results = 28
5-1 LC-VCO = 28
5-2 Charge pump with PFD = 29
5-3 Frequency synthesizer = 31
Chapter 6. Measured results = 33
6-1 LC-VCO = 33
6-2 Frequency synthesizer = 36
Chapter 7.Conclusion = 38
References = 39
List of Figures
Figure 1. Spurious emission sources for a PLL with a loop bandwidth of approximately 1MHz = 2
Figure 2. Lumped low order π-model of spiral inductor = 4
Figure 3. Tuning characteristics for the accumulation-mode MOS capacitor = 6
Figure 4. Schematic of the LC-VCO = 8
Figure 5. The conventional charge pump = 11
Figure 6. The proposed charge pump = 12
Figure 7. basic concept of the proposed charge pump = 13
Figure 8. Current mismatch of the conventional charge pump = 13
Figure 9. Charge sharing problem of the conventional and proposed charge pump = 14
Figure 10. Clock feed though problem of the conventional and proposed charge pump = 15
Figure 11. AC leakage problem of the conventional and proposed charge pump = 16
Figure 12. Fractional-N frequency synthesizer = 18
Figure 13. Phase error of Fractional-N frequency synthesizer = 18
Figure 14. Fractional-N frequency synthesizer with sigma delta modulator = 19
Figure 15. First order sigma-delta modulator (1) and its modeling (b) = 20
Figure 16. Third order cascade (MASH) sigma-delta modulator structure = 22
Figure 17. Third-order low pass loop filter = 24
Figure 18. Phase Frequency Detector = 27
Figure 19. Simulated phase noise of the LC-VCO = 28
Figure 20. Currents of the proposed and conventional charge pumps = 29
Figure 21. Output jitter of the frequency synthesizer with conventional charge pump = 31
Figure 22. Output jitter of the frequency synthesizer with the proposed charge pump = 32
Figure 23. Layout of the LC-VCO = 33
Figure 24. Tuning frequency range of the LC-VCO = 34
Figure 25. Phase noise of the LC-VCO = 34
Figure 26. Environment of testing LC-VCO = 35
Figure 27. Layout of the frequency synthesizer = 36
List of Tables
Table 1. Simulation results of the conventional and proposed charge pump = 30
Table 2. Specifications of the designed LC-VCO = 35
Table 3. Comparisons and specifications of the frequency synthesizer = 37
