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A 10b 100MS/s 27.2mW 0.8mm2 0.18um CMOS Pipeline ADC Based on Maximal Circuit Sharing Schemes

초록/요약

This work proposes a 10b 100MS/s 27.2mW 0.8mm2 0.18um CMOS ADC for WLAN such as the IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of 0.8mm2 consumes 27.2mW at 1.8V and 100MS/s.

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목차

Ⅰ.Introduction = 1
Ⅱ.Proposed ADC Architecture = 4
Ⅲ.ADC Architecture Implementation = 7
3.1 Conventional op-amp sharing techniques = 7
3.2 Proposed op-amp shring techniques in the MDACs: Version 1 = 13
3.3 Proposed op-amp sharing techniques in the MDACs: Version 2 and 3 = 20
3.4 Area- and power-efficient circuit sharing in flash ADCs = 26
Ⅳ.Prototype ADC Measurements = 35
Ⅴ.Conclusion = 43
Ⅵ.Appendix = 46
REFERENCES = 49
List of Figures
Fig. 1. Proposed 10b 100MS/s 0.18um CMOS ADC = 6
Fig. 2. Three conventional op-amp sharing techniques: (a) Shared single amplifier [8]-[9], (b) two separate amplifiers with a shared second-stage amplifier [10], and (c) shared op-amp with bias current reuse [11] = 9
Fig. 3. Op-amp with bias current reuse = 12
Fig. 4. Op-amp sharing technique proposed in the ADC version 1 removing series switches between A1 and AS: (a) with Q1 high and (b) with Q2 high = 16
Fig. 5. Op-amp sharing technique showing a memory effect: (a) with Q2 high and (b) with Q1 high = 18
Fig. 6. Op-amp sharing technique proposed for the ADC versions 2 and 3 with a timing diagram = 22
Fig. 7. (a) Op-amp employed in the MDAC of the ADC version 2 and (b) op-amp employed in the MDAC of the ADC version 3 = 23
Fig. 8. Circuit sharing schemes proposed in three 4b sub-ranging flash ADCs = 29
Fig. 9. Pre-amp sharing technique in the flash ADC2 and 3: (a) conventional pre-amp non-sharing circuit and (b) proposed pre-amp sharing circuit = 30
Fig. 10. Proposed differential difference amplifier (DDA) for pre-amplifier sharing circuits = 32
Fig. 11. Interpolated latches in the flash ADC2 and ADC3 = 33
Fig. 12. Proposed kickback-reduced dynamic latch = 34
Fig. 13. Die photograph of the proposed 10b 100MS/s 0.18um CMOS ADC (1.08mm × 0.74mm) = 37
Fig. 14. Measured DNL and INL of the prototype ADC = 38
Fig. 15. Measured FFT spectrum of the proposed ADC (1/4fs down sampled) = 39
Fig. 16. Dynamic performance of the prototype ADC: Measured SFDR and SNDR versus (a) fs and (b) fin = 40
Fig. 17. FOM comparison of the prototype ADC with the previously published ADCs = 45
Fig. 18. Signal gain reduction of the MDAC due to a parasitic feedback capacitance = 47
Fig. 19. Simulated DNL and INL of an ideal ADC with a parasitic feedback capacitance = 48
List of Tables
Table 1. Comparison of recently reported op-amp sharing techniques with the proposed op-amp sharing technique = 25
Table 2. Performance summary of the prototype ADC = 42

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