A 14b 150MS/s 140mW 2.0mm2 0.13um CMOS A/D Converter for Software Defined Radio Systems
- 발행기관 서강대학교 전자공학과 대학원
- 지도교수 이승훈
- 발행년도 2009
- 학위수여년월 2009. 2
- 학위명 석사
- 실제URI http://www.dcollection.net/handler/sogang/000000044826
- 본문언어 영어
초록/요약
This work proposes a 14b 150MS/s CMOS ADC for software defined radio systems requiring simultaneously high resolution, low power, and small chip area at high speed. The proposed calibration-free ADC employs a wide-band low-noise input SHA along with a four-stage pipelined architecture optimizing a scaling-down factor for the sampling capacitance and the input trans-conductance of amplifiers in each stage to minimize thermal noise effect and power consumption. A signal-insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of 2.0mm2 consumes 140mW at 150MS/s and 1.2V.
more목차
I.Introduction = 1
II.Proposed ADC Architecture = 5
III.Circuit Implementation and Layout Techniques = 8
3.1 Wide-band low-noise input SHA = 8
3.2 Pipelined stage scaling to optimize the overall ADC performance = 10
3.3 Highly linear 4b MDACs based on 3-D fully symmetric layout = 18
Ⅳ.Prototype ADC Measurements = 21
Ⅴ.Conclusion = 30
REFERENCES = 31
List of Figures
Fig. 1. Proposed 14b 150MS/s 0.13um CMOS ADC = 7
Fig. 2. Proposed wide-band low-noise input SHA = 9
Fig. 3. Scaling-down factors α1 and α2 = 16
Fig. 4. (a) Input-referred kT/C noise vs. scaling-down factor α1 (b) gm,tot vs. scaling-down factor α2 = 17
Fig. 5. Signal isolated 3-D fully symmetric MDAC capacitors for high matching accuracy = 20
Fig. 6. Die photograph of the prototype 14b 150MS/s ADC = 25
Fig. 7. Measured DNL and INL = 26
Fig. 8. Signal spectrum measured with a 1MHz input signal at 150MS/s = 27
Fig. 9. Measured SNDR and SFDR vs. (a) f_(s) and (b) f_(in) = 28
List of Tables
Table 1. Comparison of recently reported 14b ADCs = 4
Table 2. Performance summary of the prototype ADC = 29
